FIG. 1 illustrates a prior art clock signal distribution network 110 in an integrated circuit 101. Integrated circuit 101 is coupled to external transmission lines at respective pads, such as pad 112 for example, to receive clock and data signals from a transmitter 102 in a source synchronous (SS) system. Clock signals are received at pad 112 and recovered by a buffer 121 of integrated circuit 101. A termination resistor 118 is close to pad 112 to inhibit signal reflections at or near pad 112 as clock signals are received by integrated circuit 101. Such signal reflections may degrade signal integrity.
The recovered clock signals are distributed through wires to receivers 131, 132, 133, and 134 where they are either used directly by receiver 131, 132, 133, and/or 134 or input to a clock loop, such as a delay-locked loop (DLL), phase-locked loop (PLL), multiplying DLL, or frequency-locked loop (FLL), of receiver 131, 132, 133, and/or 134. Receiver 131, 132, 133, and/or 134 may use received clock signals, for example, to recover data signals transmitted by transmitter 102.
The distribution wires tend to be treated as dispersive resistance-capacitance (RC) wires, and buffers 122, 123, and 124 are inserted to sharpen the edges of the clock signals. Buffers 121, 122, 123, and 124 are sized to drive the total capacitance of any subsequent buffers and/or receivers. Power supply noise at buffers 121, 122, 123, and 124 changes the buffer delay and introduces timing jitter into a passed clock signal. Such jitter is generally proportional to the number of buffer(s) that have passed the clock signal. Clock timing jitter can reduce both timing and voltage margins within data links, resulting in reduced link performance or reduced maximum achievable data rate. Clock timing jitter may also require additional power to compensate for degraded signal-to-noise ratio.
Also, capacitance at pad 112 can cause a discontinuity at pad 112, resulting in reflection of some signal power back onto the external transmission line coupled to pad 112. Such reflections can attenuate or distort the clock signals and therefore can limit link performance and/or require additional power. The capacitance at pad 112 is the sum of capacitive loads near pad 112, including pad 112 itself, wiring, buffers 121, 122, 123, and 124, and receivers 131, 132, 133, and 134.
FIG. 2 illustrates a prior art data signal distribution network 210 in an integrated circuit 201. Integrated circuit 201 is coupled to external transmission lines at respective pads, such as pad 212 for example, to receive data signals from a transmitter 202. Multiple data receivers 231, 232, 233, and 234 are coupled to the same pad 212, for example, to de-multiplex data or to use separate receivers for data and clock recovery. A termination resistor 218 is close to pad 212 to inhibit signal reflections at or near pad 212 as data signals are received by integrated circuit 201. Such signal reflections may degrade signal integrity.
Similarly as with pad 112 of FIG. 1, capacitance at pad 212 can cause a discontinuity at pad 212, resulting in reflection of some signal power back onto the external transmission line coupled to pad 212. Such reflections can cause inter-symbol interference (ISI) which can limit link performance and/or require additional power. The capacitance at pad 212 is the sum of capacitive loads near pad 212, including pad 212 itself, wiring, and receivers 231, 232, 233, and 234.
The figures of the drawings are not necessarily drawn to scale.